Commercial silicon complementary metal oxide semiconductor (CMOS) technology nodes require aggressive techniques in order to address the demands of shrinking technology geometries. Of particular concern in this work is the RC time delay, whose value needs to be kept low in order to maintain signal integrity. Scaling technology nodes tend to increase RC values, though, as metal lines shrink and therefore push resistance, R, higher and thinning inter-metal dielectric layers tend to increase capacitance, C. To some extent, these affects are mitigated by improved materials, such as transition to lower dielectric-constant insulators. State-of-the-art materials can be porous such as silicon carbide hydroxide (SiCOH) and copper metal lines. However, next-generation material selections are unresolved and even the most aggressive material cannot supplant air at the material of choice for low capacitance.
Increasingly aggressive RC time delay targets for back end of line (BEOL) interconnects have forced low effective dielectric constant technologies to struggle to keep pace with the needs of smaller technology nodes. In particular, ultra-low k porous SiCOH provides a dielectric constant of 2.4. However, even this is insufficient to support upcoming technologies and so some attempts at air gap technology have been established. These air gaps help isolated metal lines from adjacent ones, lowering the effective permittivity. However, still further reduction in RC is needed to keep pace with the International Technology Roadmap for Semiconductors (ITRS) and track Moore's law. Conducting lines will actually increase resistance as they shrink in size particularly as less conductive liner layers begin to dominate the resistive losses as compared to the copper. This will further exacerbate the RC performance dilemma.